1. Field of the Invention
The present invention relates to a TLB virtualization technique in a computer virtualization technique.
2. Description of the Related Art
In recent years, a computer virtualization technique for causing plural virtual computers to simultaneously operate on a computer based on the architecture of a personal computer (hereinafter referred to as PC) has been attracting attention. Advantages such as a reduction in the number of actually operating computers and facilitation of operation and configuration changes through encapsulation of hardware are spreading in the market.
Many techniques concerning virtualization of computers such as main frames have been developed so far. However, in order to provide a high-performance, limitless, and flexible computer virtualization technique in the architecture of a PC, much contrivance is necessary not only in hardware such as a central processing unit (hereinafter referred to as CPU) but also in software for performing control.
As one of the virtualization techniques that have has been efficiently implemented, there is a translation look-aside buffer (hereinafter referred to as TLB) virtualization.
A TLB of a CPU as a premise of explanation of the background art is explained with reference to FIG. 3. When the CPU accesses a memory, the CPU specifies a position on the memory using a memory address. In a CPU including a paging mechanism, a program accesses a memory using an address on a virtual address system (hereinafter referred to as memory space) called virtual address. The CPU performs access after converting a value of the virtual address into a position on an actual memory. Usually, in order to perform the conversion at high speed and automatically, a cache memory for storing address conversion pairs is included in the CPU.
Depending on the architecture, in order to simultaneously store conversion pairs of plural memory spaces in one TLB, identifiers of memory spaces called region identifiers (hereinafter referred to as RIDs) may be used. Examples of such architecture include the Itanium (registered trademark) architecture of Intel Corporation. The present invention concerns such architecture that uses the TLB and the RIDs.
The RIDs are numbers for uniquely identifying memory spaces managed by an operating system (hereinafter referred to as an OS) on a computer. Usually, a page table (PT) corresponding to each of the memory spaces is allocated to the memory space. The page table (PT) is a correspondence table of virtual addresses and physical addresses managed by the OS. The OS registers the page table (PT) in the TLB referring to contents of the page table (PT) as required.
An example of the structure of the TLB is shown in a lower part of FIG. 3. A physical TLB includes information concerning an RID 301, a virtual address 302, and a physical address 303. A program on a CPU designates the physical address 303 on a memory by combining the RID 301 and the virtual address 302.
The CPU searches for entries in which a designated RID and a designated virtual address are equal to the RID 301 and the virtual address 302 in a TLB entry. The CPU accesses a memory indicated by the physical address 303 associated with the RID 301 and the virtual address 302. Actually, conversion of the virtual address 302 and the physical address 303 is managed for each section having a fixed size called a page rather than in the respective address units. Usually, the TLB operates as a cache for the page table. In this specification, since there is no significant reason for distinguishing the page and the respective addresses, an address refers to a general term of addresses and pages.
When there is no entry corresponding to the designated RID and the designated virtual address in the TLB entry, the CPU notifies the program of an exception signal. Usually, the OS detects an exception and registers, with reference to the page table, a set of an RID and a virtual address that cause the exception and a physical address corresponding to the virtual address in the TLB entry.
As a method with which the program designates an RID in the CPU, there is an architecture that uses region registers (hereinafter referred to as RRs). The RRs are registers exclusively used for storing RIDs of memory spaces used by a present program and are prepared in the CPU. An example of the RRs is shown in an upper part of FIG. 3. The RRs have areas for showing an RID 305 in specific bit strings of registers.
In a CPU having plural RRs, higher-order bits of a virtual address 306 may be an index number of an RR. In this system, an RID and a virtual address section of the RR designated by an RR designation section are compared with the RID 301 and the virtual address 302 of the TLB entry by a comparator 307. The physical address 303 of an entry in which the RID and the virtual address section and the RID 301 and the virtual address 302 coincide with each other is used.
The memory spaces are uniquely identified RIDs. It is likely that a different page table (PT) is used for each of the memory spaces and different address conversion is registered. In other words, even if the same virtual address is used, different physical addresses are accessed when RIDs are different. Moreover, since the OS dynamically manages the association of the RIDs and the page table, in different computers or OSs, even if the same RID and the same virtual address are designated, the RID and the virtual address may be converted into different physical addresses.
When a computer is virtualized, i.e., when plural OSs run on the same CPU, the OSs share the same TLB (TLB cache). A different page table (PT) is managed for each of the OSs and registered in the TLB in association with an independent RID. Since the association may be different for each of the OSs, when a TLB entry registered by another OS is used, the OS performs unintended conversion. In order to avoid such a situation, arbitrary processing for TLB resources is indispensable in an environment in which plural OSs run on a single CPU in parallel.
As a method of arbitrating TLB resources in the architecture described above, a method called RID partitioning is used in ISSN 1535-864X, Intel (registered trademark) Virtualization Technology Volume 10 Issue 03 (hereinafter referred to as Non-Patent Document 1). In this method, an RID is divided into a bit range for identifying a virtual computer and a bit range for identifying a memory space in the virtual computer. An OS can change only the bit range for identifying a memory space in the latter half.